9.10 8086 Interrupts
The 8086 assigns every interrupt a type code so that the 8086 can identify it. Interrupts can be initiated by external devices or internally by software instructions or by exceptional conditions such as attempting to divide by zero.
9.10.1 Predefined Interrupts
The first five interrupt types are reserved for specific functions.
The interrupt vectors for these five interrupts are predefined by Intel. The user must provide the desired IP and CS values in the interrupt pointer table. The user may also initiate these interrupts through hardware or software. If a predefined interrupt is not used in a system, the user may assign some other function to the associated type.
The 8086 is automatically interrupted whenever a division by zero is attempted.
This interrupt is nonmaskable and is implemented by Intel as part of the execution of the divide instruction.
When the TF (trap flag) is set by an instruction, the 8086 goes into single-step mode. The TF can be cleared to zero as follows:
Note here that O[BP] rather than [BP] is used because BP cannot normally be used without displacement in the 8086 assembler. Now, to set TF, the AND instruction just shown should be replaced by OR 0 [BP],OlOOH. Once TF is set to 1, the 8086 automatically generates a type 1 interrupt after execution of each instruction. The user can write a service routine at the interrupt address vector to display memory locations and/or register to debug a program. Single-step mode is nonmaskable and cannot be enabled by the STI (enable interrupt) or disabled by the CLI (disable interrupt) instruction.
The nonmaskable interrupt is initiated via the 8086 NMI pin. It is edge triggered (LOW to HIGH) and must be active for two clock cycles to guarantee recognition. It is normally used for catastrophic failures such as a power failure. The 8086 obtains the interrupt vector address by automatically executing the INT2 (type 2) instruction internally.
The type 3 interrupt is used for breakpoints and is nonmaskab1e. The user inserts the 1-byte instruction INT3 into a program by replacing an instruction. Breakpoints are useful for program debugging.
The interrupt on overflow is a type 4 interrupt. This interrupt occurs if the overflow flag (OF) is set and the INTO instruction is executed. The overflow flag is affected, for example, after execution of a signed arithmetic (such as IMUL, signed multiplication) instruction. The user can execute an INTO instruction after the IMUL. If there is an overflow, an error service routine written by the user at the type 4 interrupt address vector is executed.
9.10.2 Internal Interrupts
The user can generate an interrupt by executing an interrupt instruction INTnn. The INTnn instruction is not maskable by the interrupt enable flag (IF). The INTnn instruction can be used to test an interrupt service routine for external interrupts. Type codes 32-255 can be used; type codes 5 through 31 are reserved by the Intel for future use. If a predefined interrupt is not used in a system, the associate type code can be utilized with the INTnn instruction to generate software (internal) interrupts.
9.10.3 External Maskable Interrupts
The 8086 maskable interrupts are initiated via the INTR pin. These interrupts can be enabled or disabled by STI (IF= 1) or CLI (IF= 0), respectively. IfiF = 1 and INTR active (HIGH) without occurrence of any other interrupts, the 8086, after completing the current instruction, generates INTA LOW twice, each time for about one cycle.
INTA is only generated by the 8086 in response to INTR, as shown in Figure M9.24. The interrupt acknowledge sequence includes two INTA cycles separated by two clock cycles. ALE is also generated by the 8086 and will load the address latches with indeterminate information. The first INTA bus cycle indicates that an interrupt acknowledge cycle is in progress and allows the system to be ready to place the interrupt type code on the next INTA bus cycle. The 8086 does not obtain the information from the bus during the first cycle. The external hardware must place the type code on the lower half of the 16-bit data bus (D0-D7) during the second cycle.
In the minimum mode, the M/IO is LOW, indicating I/O operation during theINTA bus cycles. The 8086 internal LOCK signal is also LOW from T2 of the first bus cycle until T2 of the second bus cycle to keep the BIU from accepting a hold request between the two INTA cycles. Figure 9.25 shows a simplified interconnection between the 8086 and 74LS244 for servicing the INTR. INTA enables the 74LS244 to place type code nn on the 8086 data bus. In the maximum mode, the status lines S0-S2 will generate the INTA output.
9.10.4 Interrupt Procedures
Once the 8086 has the interrupt type code (via the bus for hardware interrupts, from software interrupt instructions INTnn, or from the predefined interrupts), the type code is multiplied by 4 to obtain the corresponding interrupt vector in the interrupt vector table. The 4 bytes of the interrupt vector are the least significant byte of the instruction pointer, the most significant byte of the instruction pointer, the least significant byte of the code segment register, and the most significant byte of the code segment register. During the transfer of control, the 8086 pushes the flags and current code segment register and instruction pointer onto the stack. The new CS and IP values are loaded. Flags TF and IF are then cleared to zero. The CS and IP values are read by the 8086 from the interrupt vector table. No segment registers are used when accessing the interrupt pointer table. S4 S3 has the value 102 to indicate no segment register selection.
9.10.5 Interrupt Priorities
As far as the 8086 interrupt priorities are concerned, the single-step interrupt has the highest priority, followed by NMI, followed by the software interrupts. This means that a
simultaneous NMI and single-step interrupt will cause the NMI service routine to follow the single step; a simultaneous software interrupt and single step interrupt will cause the software interrupt service routine to follow the single step; and a simultaneous NMI and software interrupt will cause the NMI service routine to be executed prior to the software interrupt service routine. The INTR is maskable and has the lowest priority. A priority interrupt controller such as the 8259A can be used with the 8086 INTR to provide eight levels of interrupts. The 8259A has built-in features for expansion of up to 64levels with additional 8259s. The 8259A is programmable and can be readily used with the 8086 to obtain multiple interrupts from the single 8086 INTR pin.
9.10.6 Interrupt Pointer Table
The interrupt pointer table provides interrupt address vectors (IP and CS contents) for all the interrupts. There may be up to 256 entries for the 256 type codes. Each entry consists of two addresses, one for storing IP and the other for storing CS. Note that in the 8086 each interrupt address vector is a 20-bit address obtained from IP and CS.
To service an interrupt, the 8086 calculates the two addresses in the pointer table where IP and CS are stored for a particular interrupt type as follows:
The table address for IP = 4 x nn and the table address for CS = 4 x nn + 2. For example, consider INT2:
Address for IP = 4 x 2 = 00008H
Address for CS = 00008 + 2 = 0000AH
The values ofiP and CS are loaded from location 00008H and OOOOAH in the pointer table. Similarly, the IP and CS addresses for other INTnn are calculated, and their values are obtained from the contents of these addresses in the pointer table (Table 9.13). The 8086 interrupt vectors are defined as follows:
Interrupt service routines should be terminated with an IRET (interrupt return) instruction, which pops the top three stack words into the IP, CS, and flags, thus returning control to the right place in the main program.
9.12 8086 DMA
When configured in minimum mode (MN/MX HIGH) the 8086 provides HOLD and HLDA (hold acknowledge) signals to control the system bus for DMA applications. In this type ofDMA, the peripheral device can request the DMA transfer via the DMA request (DRQ) line connected to a DMA controller chip such as the 8257. In response to this request, the 8257 sends a HOLD signal to the 8086. The 8257 then waits for the HLDA signal from the 8086. On receipt of this HLDA, the 8257 sends a DMACK signal to the peripheral device. The 8257 then takes over the bus and controls data transfer between the RAM and peripheral device. On completion of data transfer, the 8257 returns control to the 8086 by disabling the HOLD and DMACK signals.
Example 9.21
In Figure 9.26, an 8086-based microcomputer is required to implement a voltmeter to measure voltage in the range 0 to 5 V and display the result in two decimal digits: one integer part and one fractional part. The microcomputer is required to start the AID converter at the falling edge of a pulse via bit 0 of Port C. When the conversion is completed, the A/D's "conversion complete" signal will go HIGH. During the conversion, the AID's "conversion complete" signal stays LOW. Use the 8255 control register= FEH, Port A= F8H, Port B = FAH, and Port C = FCH.
Using programmed I/O, the microcomputer is required to poll the AID's "conversion complete" signal. When the conversion is completed, the microcomputer will send a LOW of the AID converter's "output enable" line via bit 1 to port C and then input the 8-bit output from AID via port B and display the voltage (0 to 5 V) in two decimal digits (one integer and one fractional) via port A on two TIL 311 displays. Note that the TIL 311 has an on-chip BCD to seven-segment decoder. The microcomputer will output each decimal digit on the common lines (bits 0-3 of port A) connected to the DCBA inputs of the displays. Each display will be enabled by outputting LOW on each LATCH line
in sequence (one after another) so that the input voltage Vx (0 to 5 V) will be displayed with one integer part and fractional part. Write an 8086 assembly language program to accomplish this.
Using interrupt I/O (both NMI and INTR), repeat the task. Write the main program to initialize the 8255 control register and start the A/D. The service routine will input the AID data, display the result, and stop. Write an 8086 assembly language program for the main program and the service routine. Use the memory map of your choice. Write the service routines for both NMI and INTR starting at IP=2000H, CS=1000H. Use 8086 assembler directive such as ORG CS:IP for the HP (Hewlett-Packard) 64XXX microcomputer development system in the following programs.
Solution
Because the maximum decimal value that can be accommodated in 8 bits is 255 10 (FF16), the maximum voltage of 5 V will be equivalent to 25510• This means the display in decimal is given by
(b) UsingNMI
In Figure 9.26, connect the "conversion complete" to 8086 NMI; all other connections in Figure 9.26 will remain unchanged. Note that all addresses selectable by the user are arbitrarily chosen in the following. The main program in 8086 assembly language is
(c) Using INTR
All connections in Figure 9.26 will be same except AID's "conversion complete" to 8086 INTR as shown in Figure 9.27. All other connections in Figure 9.26 will remain unchanged. INT FFH is used. In response to INTR, the 8086 pushes IP and SR onto the stack, and generates LOW on INTA. An octal buffer such as 74LS244 can be enabled by this INTA to transfer FF 16 in this case (can be entered via eight DIP switches connected to+ 5 V through a I KQ resistor) to the input of the octal buffer. The output of the octal buffer is connected to the demultiplexed D0-D7 lines of the 8086. The 8086 executes INT FFH and goes to the interrupt pointer table to load the contents of physical addresses 003FCH (logical address:
CS = OOOOH, IP = 03FCH) and 003FEH (logical address: CS = OOOOH, IP = 03FEH) to obtain IP and CS for the service routine respectively. Suppose that it is desired to write the service routine at IP = 2000H and CS = 1 OOOH; these IP and CS values must be stored at addresses 003FCH and 003FEH respectively. All user selectable addresses are arbitrarily chosen. The main program in 8086 assembly language is
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