One application area the 8051 is designed to fill is that of machine control. A large part of machine control concerns sensing the on-off states of external switches, making decisions based on the switch states. and then turning external circuits on or off.
Single point sensing and control implies a need for byte and bit opcodes that operate on data using Boolean operators. All 8051 RAM areas, both data and SFRs, may be manipulated using byte opcodes. Many of the SFRs, and a unique internal RAM area that is bit addressable, may be operated upon at the individual bit level. Bit operators are notably efficient when speed of response is needed. Bit operators yield compact program code that enhances program execution speed.
The two data levels, byte or bit, at which the Boolean instructions operate are shown in the following table:
| BOOLEAN OPERATOR | 8051 MNEMONIC |
| AND | ANL (AND logical) |
| OR | ORL (OR logical) |
| XOR | XRL (exclusive OR logical) |
| NOT | CPL (complement) |
There are also rotate opcodes that operate only on a byte, or a byte and the carry flag, to permit limited 8- and 9-bit shift-register operations. The following table shows the rotate opcodes:
| Mnemonic | Operation |
| RL | Rotate a byte to the left; the Most Significant Bit (MSB) becomes the Least Significant Bit (LSB) |
| RLC | Rotate a byte and the carry bit left; the carry becomes the LSB, the MSB becomes the carry |
| RR | Rotate a byte to the right; the LSB becomes the MSB |
| RRC | Rotate a byte and the carry to the right; the LSB becomes the carry, and the carry the MSB |
| SWAP | Exchange the low and high nibbles in a byte |
Byte-Level Logical Operations
The byte-level logical operations use all four addressing modes for the source of a data byte. The A register or a direct address in internal RAM is the destination of the logical operation result.
Keep in mind that all such operations are done using each individual bit of the destination and source bytes. These operations, called byte-level Boolean operations because tlfe entire byte is affected, are listed in the following table:
| Mnemonic | Operation |
| ANL A,#n | AND each bit of A with the same bit of immediate number n; put the results in A |
| ANL. A.add | AND each bit of A with the same bit of the direct RAM address; put the results in A |
| ANLA,Rr | AND each bit of A with the same bit of register Rr; put the results in A AND each bit of A with the same bit of the contents of the RAM address contained in Rp; put the results in A |
| ANL A,@Rp | AND each bit of A with the direct RAM address; put the results in the direct RAM address |
| ANL add.A | AND each bit of the RAM address with the same bit in the number n; put the result in the RAM address |
| ANL add,#n | OR each bit of A with the same bit of n; put the results in A |
| ORL A,#n | OR each bit of A with the same bit of the direct RAM address; put the results in A |
| ORL A,add | OR each bit of A with the same bit of register Rr; put the results in A OR each bit of A with the same bit of the contents of the RAM address contained in Rp; put the results in A |
| ORL A,Rr | OR each bit of A with the direct RAM address; put the results in the direct RAM address |
| ORL A,@Rp | OR each bit of the RAM address with the same bit in the number n; put the result in the RAM address |
| ORL add.A | XOR each bit of A with the same bit of n; put the results in A |
| ORL add,#n | XOR each bit of A with the same bit of the direct RAM address; put the results in A |
| XRL A,#n | XOR each bit of A with the same bit of register Rr; put the results in A XOR each bit of A with the same bit of the contents of the RAM address contained in Rp; put the results in A |
| XRL A,add | XOR each bit of A with the direct RAM address; put the results in the direct RAM address |
| XRL A,Rr | Operation |
| XRL A,@Rp | AND each bit of A with the same bit of immediate number n; put the results in A |
| XRL add.A | AND each bit of A with the same bit of the direct RAM address; put the results in A |
| XRL add,#n | XOR each bit of the RAM address with the same bit in the number n; put the result in the RAM address |
| CLRA | Clear each bit of the A register to zero |
| CPL A | Complement each bit of A; every I becomes a 0, and each 0 becomes a 1 |
Note that no flags are affected unless the direct RAM address is the PSW.
Many of these byte-level operations use a direct address, which can include the port SFR addresses, as a destination. The normal source of data from a port is the port pins; the normal destination for port data is the port latch. When the destination of a logical operation is the direct address of a port, the latch register, not the pins, is used both as the source for the original data and then the destination for the altered byte of data. Any port operation that must first read the source data, logically operate on it, and then write it back to the source (now the destination) must use the latch. Logical operations that use the port as a source, but not as a destination, use the pins of the port as the source of the data.
For example, the port 0 latch contains FFh, but the pins are all driving transistor bases and are close to ground level. The logical operation
ANL PO,#0 Fh
which.is designed to turn the upper nibble transistors off, reads FFh from the latch, ANDs it with 0Fh to produce 0Fh as a result, and then writes it back to the latch to turn these transistors off. Reading the pins produces the result 00h, turning all transistors off, in error. But, the operation
ANL A ,P0
produces A = 00h by using the port 0 pin data, which is 00h.
The following table shows byte-level logical operation examples:
| Mnemonic | Operation |
| MOV A,#0FFh | A= FF h |
| MOV R0,#77h | R0= 77h |
| ANL A,R0 | A= 77h |
| MOV 15h,A | 15h = 77h |
| CPL A | A= 88h |
| ORL 15h,#88h | 15h = FFh |
| XRL A,15h | A= 77h |
| XRL A,R0 | A= 00h |
| ANL A,15h | A= 00h |
| ORL A,R0 | A= 77h |
| CLR A | A= 00h |
| XRL 15h,A | 15h = FFh |
| XRL A.R0 | A= 77h |
Note that instructions that can use the SFR port latches as destinations are ANL, ORL, and XRL.
CAUTION
If the direct address destination is one of the port SFRs, the data latched in the SFR, not the pin data, is used.
No flags are affected unless the direct address is the PSW. Only internal RAM or SFRs may be logically manipulated.
Bit-Level Logical Operations
Certain internal RAM and SFRs can be addressed by their byte addresses or by the address of each bit within a byte. Bit addressing is very convenient when you wish to alter a single bit of a byte, in a control register for instance, without having to wonder what you need to do to avoid altering some other crucial bit of the same byte. The assembler can also equate bit addresses to labels that make the program more readable. For example, bit 4 of TCON can become TR0, a label for the timer 0 run bit.
The ability to operate on individual bits creates the need for an area of RAM that contains data addresses that hold a single bit. Internal RAM byte addresses 20h to 2Fh serve this need and are both byte and bit addressable. The bit addresses are numbered from 00h to 7Fh to represent the 12Sd bit addresses (16d bytes x S bits) that exist from byte addresses 20h to 2Fh. Bit 0 of byte address 20h is bit address 00h, and bit 7 of byte address 2Fh is bit address 7Fh. You must know your bits from your bytes to take advantage of this RAM area.
Internal RAM Bit Addresses
The availability of individual bit addresses in internal RAM makes the use of the RAM very efficient when storing bit information. Whole bytes do not have to be used up to store one or two bits of data.
The correspondence between byte and bit addresses are shown in the following table:
| BYTE ADDRESS (HEX) | BIT ADDRESSES (HEX) |
| 20 | 00-07 |
| 21 | 08-0F |
| 22 | 10-17 |
| 23 | 18-lF |
| 24 | 20-27 |
| 25 | 28-2F |
| 26 | 30-37 |
| 27 | 38-3F |
| 28 | 40-47 |
| 29 | 48-4F |
| 2A | 50-57 |
| 28 | 58-5F |
| 2C | 60-67 |
| 20 | 68-6F |
| 2E | 70-77 |
| 2F | 78-7F |
Interpolation of this table shows, for example, the address of bit 3 of internal RAM byte address 2Ch is 63h, the bit address of bit 5 of RAM address 21 h is 00h, and bit address 47h is bit 7 of RAM byte address 28h.
SFR Bit Addresses
All SFRs may be addressed at the byte level by using the direct address assigned to it, but not all of the SFRs are addressable at the bit level. The SFRs that are also bit addressable form the bit address by using the five most significant bits of the direct address for that SFR, together with the three least significant bits that identify the bit position from position 0 (LSB) to 7 (MSB).
The bit-addressable SFR and the corresponding bit addresses are as follows:
| SFR | DIRECT ADDRESS (HEX) | BIT ADDRESSES (HEX) |
| A | OED | OEO-OE7 |
| 6 | OFO | OFO-OF7 |
| IE | OAS | OAS-OAF |
| IP | 06S | 06S-06F |
| PO | so | SO-S7 |
| Pl | 90 | 90-97 |
| P2 | OAO | OAO-OA7 |
| P3 | 060 | 060-067 |
| PSW | ODO | ODO-OD7 |
| TCON | SS | SS-SF |
| SCON | 9S | 9S-9F |
The patterns in this table show the direct addresses assigned to the SFR bytes all have bits 0-3 equal to zero so that the address of the byte is also the address of the LSB. For example, bit 0E3h is bit 3 of the A register. The carry flag, which is bit 7 of the PSW, is bit addressable as 0D7h. The assembler can also "understand" more descriptive mnemonics, such as P0.5 for bit 5 of port 0, which is more formally addressed as 85h.
Figure 4. I shows all the bit-addressable SFRs and the function of each addressable bit. (Refer to Chapter 2 for more detailed descriptions of the SFR bit functions.)
Bit-Level Boolean Operations
The bit-level Boolean logical opcodes operate on any addressable RAM or SFR bit. The carry flag (C) in the PSW special-function register is the destination for most of the opcodes because the flag can be tested and the program flow changed using instructions covered in Chapter 6.
The following table lists the Boolean bit-level operations.
| Mnemonic | Operation |
| ANL C,b | AND C and the addressed bit; put the result in C |
| ANL C,/b | AND C and the complement of the addressed bit; put the result in C; the addressed bit is not altered |
| ORL C,b | OR C and the addressed bit; put the result in C |
| ORLC,/b | OR C and the complement of the addressed bit; put the result in C; the addressed bit is not altered |
| CPLC | Complement the C flag |
| CPL b | Complement the addressed bit |
| CLRC | Clear the C flag to zero |
| CLR b | Clear the addressed bit to zero |
| MOV C,b | Copy the addressed bit to the C flag |
| MOV b,C | Copy the C flag to the addressed bit |
| SETB C | Set the flag to one |
| SETB b | Set the addressed bit to one |
Note that no flags, other than the C flag, are affected, unless the flag is an addressed bit.
As is the case for byte-logical operations when addressing ports as destinations, a port bit used as a destination for a logical operation is part of the SFR latch, not the pin. A port bit used as a source only is a pin, not the latch. The bit instructions that can use a SFR latch bit are: CLR, CPL, MOY, and SETB.
FIGURES 4.1 Bit-Addressable Control Registers
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CY | AC | F0 | RSI | RS0 | 0V | Resarved | P |
PROGRAM STATUS WORD (PSW) SPECIAL FUNCTION REGISTER. BIT ADDRESSES D0h to D7h.
| Bit | Function |
| 7 | Carry flag |
| 6 | Auxiliary carry flag |
| 5 | User flag 0 |
| 4 | Register bank select bit 1 |
| 3 | Register bank select bit 0 |
| 2 | Overflow flag |
| 1 | Not used (reserved for future) |
| 0 | Parity flag |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EA | Reserved | Reserved | ES | ET1 | EX 1 | ET0 | EX0 |
INTERRUPT ENABLE (IE) SPECIAL FUNCTION REGISTER. BIT ADDRESSES A8h TO AFh.
| Bit | Function |
| 7 | Disables all interrupts |
| 6 | Not used (reserved for future) |
| 5 | Not used (reserved for future) |
| 4 | Serial port interrupt enable |
| 3 | Timer 1 overflow interrupt enable |
| 2 | External interrupt 1 enable |
| 1 | Timer 0 interrupt enable |
| 0 | External interrupt 0 enable |
EA disables all interrupts when cleared to 0; if EA = 1 then each individual interrupt will be enabled if 1, and disabled if 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| * | * | Reserved | PS | PT1 | PX1 | PT0 | PX0 |
INTERRUPT PRIORITY (IP) SPECIAL FUNCTION REGISTER. BIT ADDRESSES B8h to BFh.
| Bit | Function |
| 7 | Not implemented |
| 6 | Not implemented |
| 5 | Not used (reserved for future) |
| 4 | Serial port interrupt priority |
| 3 | Timer 1 interrupt priority |
| 2 | External interrupt 1 priority |
| 1 | Timer 0 interrupt priority |
| 0 | External interrupt 0 priority |
The priority bit may be set to 1 (highest) or 0 (lowest).
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TF1 | TR1 | TF0 | TR0 | IE1 | IT1 | IE0 | IT0 |
TIMER/COUNTER CONTROL (TCON) SPECIAL FUNCTION REGISTER. BIT ADDRESSES 88h to 8Fh.
| Bit | Function |
| 7 | Timer 1 overflow flag |
| 6 | Timer run control |
| 5 | Timer 0 overflow flag |
| 4 | Timer 0 run control |
| 3 | External interrupt 1 edge flag |
| 2 | External interrupt 1 mode control |
| 1 | External interrupt 0 edge flag |
| 0 | External interrupt 0 mode control |
All flags can be set by the indicated hardware action; the flags are cleared when interrupt is serviced by the processor.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SM0 | SM1 | SM2 | REN | TBB | RBB | TI | RI |
SERIAL PORT CONTROL (SCON) SPECIAL FUNCTION REGISTER. BIT ADDRESSES 98h to 9Fh.
| Bit | Function |
| 7 | Serial port mode bit 0 |
| 6 | Serial port mode bit 1 |
| 5 | Multiprocessor communications enable |
| 4 | Receive enable |
| 3 | Transmitted bit in modes 2 and 3 |
| 2 | Received bit in modes 2 and 3 |
| 1 | Transmit interrupt flag |
| 0 | Receive interrupt flag |
Bit-level logical operation examples are shown in the following table:
| Mnemonic | |
| SETB 00h | Operation |
| MOV C,00h | Bit 0 of RAM byte 20h = 1 |
| MOV 7Fh,C | C=1 |
| ANL C,/00h | Bit 7 of RAM byte 2Fh = 1 |
| ORL C,00h | C = 0; bit 0 of RAM byte 20h =1 |
| CPL 7Fh | C=1 |
| CLR C | Bit 7 of RAM byte 2Fh = 0 |
| ORL C,/7Fh | C=0 |
CAUTION
Only the SFRs that have been identified as bit addressable may be used in bit operations. If the destination bit is a port bit, the SFR latch bit is affected, not the pin.
ANL C,/b and ORL C,/b do not alter the addressed bit b,
Labels: 8051 Logical Operations