This section describes the clock generator (8284A) and the RESET signal, and introduces the READY signal for the 8086/8088 microprocessors. (The READY signal and its associated circuitry are treated in detail in Section 9–5.)
The 8284A is an ancillary component to the 8086/8088 microprocessors. Without the clock gen- erator, many additional circuits are required to generate the clock (CLK) in an 8086/8088-based system. The 8284A provides the following basic functions or signals: clock generation, RESET synchronization, READY synchronization, and a TTL-level peripheral clock signal. Figure 9–2 illustrates the pin-out of the 8284A clock generator.
Pin Functions. The 8284A is an 18-pin integrated circuit designed specifically for use with the 8086/8088 microprocessor. The following is a list of each pin and its function.
RDY1 and RDY2 The bus ready inputs are provided, in conjunction with the AEN1 and AEN2 pins, to cause wait states in an 8086/8088-based system.
The ready synchronization selection input selects either one or two stages of synchronization for the RDY1 and RDY2 inputs.
READY Ready is an output pin that connects to the 8086/8088 READY input. This signal is synchronized with the RDY1 and RDY2 inputs.
X1 and X2 The crystal oscillator pins connect to an external crystal used as the timing source for the clock generator and all its functions.
The frequency/crystal select input chooses the clocking source for the 8284A. If this pin is held high, an external clock is provided to the EFI input pin; if it is held low, the internal crystal oscillator provides the timing signal. The external frequency input is used when the F/C pin is pulled high. EFI supplies the timing whenever the F/C pin is high.
CLK The clock output pin provides the CLK input signal to the 8086/8088 microprocessors and other components in the system. The CLK pin has an output signal that is one third of the crystal or EFI input frequency, and has a 33% duty cycle, which is required by the 8086/8088.
PCLK The peripheral clock signal is one sixth the crystal or EFI input frequency, and has a 50% duty cycle. The PCLK output provides a clock signal to the peripheral equipment in the system.
OSC The oscillator output is a TTL-level signal that is at the same frequency as the crystal or EFI input. The OSC output provides an EFI input to other 8284A clock generators in some multiple-processor systems.
The reset input is an active-low input to the 8284A. The RES pin is often connected to an RC network that provides power-on resetting.
RESET The reset output is connected to the 8086/8088 RESET input pin.
CSYNC The clock synchronization pin is used whenever the EFI input provides synchronization in systems with multiple processors. If the internal crystal oscillator is used, this pin must be grounded.
GND The ground pin connects to ground.
VCC This power supply pin connects to +5.0 V with a tolerance of ±10%.
The 8284A is a relatively easy component to understand. Figure 9–3 illustrates the internal tim- ing diagram of the 8284A clock generator.
Operation of the Clock Section. The top half of the logic diagram represents the clock and synchronization section of the 8284A clock generator. As the diagram shows, the crystal oscillator has two inputs: X1 and X2. If a crystal is attached to X1 and X2, the oscillator generates a square- wave signal at the same frequency as the crystal. The square-wave signal is fed to an AND gate and also to an inverting buffer that provides the OSC output signal. The OSC signal is sometimes used as an EFI input to other 8284A circuits in a system.
An inspection of the AND gate reveals that when F/C is a logic 0, the oscillator output is steered through to the divide-by-3 counter. If F/C is a logic 1, then EFI is steered through to the counter.
The output of the divide-by-3 counter generates the timing for ready synchronization, a signal for another counter (divide-by-2), and the CLK signal to the 8086/8088 microprocessor. The CLK signal is also buffered before it leaves the clock generator. Notice that the output of the first counter feeds the second. These two cascaded counters provide the divide-by-6 output at PCLK, the peripheral clock output.
Operation of the Reset Section. The reset section of the 8284A is very simple: It consists of a Schmitt trigger buffer and a single D-type flip-flop circuit. The D-type flip-flop ensures that the timing requirements of the 8086/8088 RESET input are met. This circuit applies the RESET signal to the microprocessor on the negative edge (1-to-0 transition) of each clock. The 8086/8088 microprocessors sample RESET at the positive edge (0-to-1 transition) of the clocks; therefore, this circuit meets the timing requirements of the 8086/8088.
Refer to Figure 9–4. Notice that an RC circuit provides a logic 0 to the RES input pin when power is first applied to the system. After a short time, the RES input becomes a logic 1 because the capacitor charges toward +5.0 V through the resistor. A pushbutton switch allows the microprocessor to be reset by the operator. Correct reset timing requires the RESET input to come a logic 1 no later than four clocks after system power is applied, and to be held high for at
least 50 μs. The flip-flop makes certain that RESET goes high in four clocks, and the RC time constant ensures that it stays high for at least 50 μs.
