MEMORY INTERFACE:80386DX AND 80486 (32-BIT) MEMORY INTERFACE

80386DX AND 80486 (32-BIT) MEMORY INTERFACE

As with 8- and 16-bit memory systems, the microprocessor interfaces to memory through its data bus and control signals that select separate memory banks. The only difference with a 32-bit memory system is that the microprocessor has a 32-bit data bus and four banks of memory, instead of one or two. Another difference is that both the 80386DX and 80486 (both SX and DX) contain a 32-bit address bus that usually requires PLD decoders instead of integrated decoders because of the sizable number of address bits.

Memory Banks

The memory banks for both the 80386DX and 80486 microprocessors are illustrated in Figure 10–33. Notice that these large memory systems contain four 8-bit-wide banks that each contain up to 1G bytes of memory. Bank selection is accomplished by the bank selection signals BE3, BE2, BE1, and BE0. If a 32-bit number is transferred, all four banks are selected; if a 16-bit number is transferred, two banks (usually BE3 and BE2 or BE1 and BE0) are selected; and if 8 bits are transferred, a single bank is selected.

As with the 8086/80286/80386SX, the 80386DX and 80486 require separate write strobe signals for each memory bank. These separate write strobes are developed, as illustrated in Figure 10–34, by using a simple OR gate or other logic component.

32-Bit Memory Interface

As can be gathered from the prior discussion, a memory interface for the 80386DX or 80486 requires that we generate four bank write strobes and decode a 32-bit address. There are no integrated decoders, such as the 74LS138, that can easily accommodate a memory interface for the 80386DX or 80486 microprocessors. Note that address bits A0 and A1 are don’t cares when 32- bit-wide memory is decoded. These address bits are used within the microprocessor to generate the bank enable signals. Notice that the address bus connection A2 connects to memory address pin A0. This occurs because there is no A0 or A1 pin on the 80486 microprocessor.

Figure 10–35 shows a 512K × 8 SRAM memory system for the 80486 microprocessor. This interface uses eight 64K × 8 SRAM memory devices, a PLD, and an OR gate. The OR gate is required because of the number of address connections found on the microprocessor. This sys- tem places the SRAM memory at locations 02000000H–0203FFFFH. The program for the PLD device is found in Example 10–9.

Although not mentioned in this section of the text, the 80386DX and 80486 microprocessors operate with very high clock rates that usually require wait states for memory access. Access time calculations for these microprocessors are discussed in Chapters 17 and 18. The interface provides a signal used with the wait state generator that is not illustrated in this section of the text. Other devices with these higher speed microprocessors are cache memory and interleaved memory sys- tems. These are also presented in Chapter 17 with the 80386DX and 80486 microprocessors.