8051 microcontrollers

8289 Bus Arbiter 1. Dra w the pin connection diagram of 8289. Ans. The following is the connection diagram of 8289. 3. Explai n how 8289 bus arbiter operates in a multi-master system. Ans. In MAX mode 8086 processor is interfaced with 8289 bus arbiter, along with bus controller IC 8288 in a multi-master system bus configuration. When the processor does not use the system buses, bus arbiter forces the bus driver output in the high impedance state. The bus arbiter allows the bus controller, the data transreceivers and the address latches to access the system bus. On a multi-master system bus, the bus arbiter is responsible for avoiding the bus contention between bus masters. 4. Ho w the arbitration between bus masters works? Ans. The bus is transferred to a higher priority master when the lower priority master completes its task. Lower priority masters get the bus when a higher priority one does not seek to access the bus, although with the help of ANYRQST input, the bus...

8089 I/O Processor 1. Dra w the pin connection diagram of 8089. Ans. The pin connection diagram of 8089 is shown in Fig. 19c.1. 2. Dra w the functional block diagram of 8089. Ans. The functional block diagram of 8089 is shown in Fig. 19c.2. 3. Writ e down the characteristic features of 8089. Ans. The characteristic features of 8089 are as follows: z Very high speed DMA capability—I/O to memory, memory to I/O, memory to memory and I/O to I/O. z 1 MB address capability. z iAPX 86, 88 compatible. z Supports local mode and remote mode I/O processing. z Allows mixed interface of 8-and 16-bit peripherals, to 8-and 16-bit processor buses. z Multibus compatible system interface. z Memory based communications with CPU. z Flexible, intelligent DMA functions, including translation, search, word assembly/ disassembly. z Supports two I/O channels. 4. Indicat e the data transfer rate of 8089 IOP. Ans. On each of the two channels of 8089, data can be transferred ...

8087 Numeric Data Processor 1. Dra w the pin connection diagram of 8087. Ans. The pin diagram of 8087 is shown in Fig. 19b.1. 2. Wha t are the characteristics of 8087 NDP? Ans. The following are the characteristic features of 8087 NDP: z It can add arithmetic, trigonometric, exponential and logarithmic instructions to the 8086 instruction set for all data types. z 8087 can handle seven data types. These are : 16, 32, 64-bit integers, 32, 64, 80-bit floating point and 18–digit BCD operands. z It has three clock speeds: 5 MHz (8087), 8 MHz (8087–2) and 10 MHz (8087–1) z It can add 8 × 80-bit individually addressable register stack to the 8086 architecture. z Multibus system compatiable interface. z Seven numbers built-in exception handling functions. z Compatible with IEEE floating point standard 754. z It adds 68 mnemonics to the 8086 instruction set. z Fabricated with HMOS III technology and packaged in a 40-pin cerdip package. 3. Dra w the architecture ...

8288 Bus Controller 1. Dra w the pin diagram of 8288. 2. Dra w the functional block diagram of 8288. Ans. The functional block diagram of 8288 is shown in Fig. 19a.2. 3. I s 8288 always used with 8086? Ans. No, the bus controller IC 8288 is used with 8086 when the latter is used in MAX mode. 4. Wha t are the inputs to 8288? Ans. There are two sets of inputs—the first set is the status inputs S0 , S1 and S2 . The second set is the control inputs having the following signals: CLK, AEN, CEN and IOB. 5. Wha t are the output signals from 8288? Ans. There are two sets of output signals—Multibus command signals and the second set includes the bus control signals—Address Latch, Data Transreceiver and Interrupt Control Signals. The multibus command Signals are the Conventional MEMR, MEMW, IOR and IOW signals which have been renamed as MRDC, MWTC, IORC, IOWC, where the suffix ‘C’ stands for command. INTA signal is also included in this. Two more signals— AMWC and AIOWC ...

8086 Interrupts 1. Ho w many interrupts can be implemented using 8086 µ P? Ans . A total of 256 interrupts can be implemented using 8086 µP. 2. Mentio n and tabulate the different types of interrupts that 8086 can implement. Ans. 8086 µP can implement seven different types of interrupts. z NMI and INTR are external interrupts implemented via Hardware . z INT n, INTO and INT3 (breakpoint instruction) are software interrupts implemented through Program. z The ‘divide-by-0’ and ‘Single-step’ are interrupts initiated by CPU. Table 18.1 shows the seven interrupt types implemented by 8086. 3. Distinguis h between the two hardware interrupts of 8086. Ans. The distinction between the two hardware interrupts of 8086 are as follows, shown in Table 18.2. T able18.2 : Comparison of NMI and INTR interrupts NMI INTR 1. Non-maskable type. 2. Higher priority. ...