8051 microcontrollers

1. if a memory chip is organized in a 4096 x 1 format, specify the number of registers in the chip and the number of bits stored by each register. 2. if 16K x 1 memory chips are used in a memory design, how many chips are required to design 64K-byte memory? 3. Specify the number of chips necessary to design 8K-byte memory with 1024 x 4 memory chips. 4. In Figure 1 . generate the equivalent M͞S͞EL 0 " signal by using a4-input NAND gate (and inverters) to decode the address lines A 15 -A 13 and the M͞R͞E͞Q. 5. Generate the signal equivalent to the M͞S͞E͞L 0 signal in Figure 7 using the 74LS139. which bas two 2-to-4 decoders in the package. 6. In Figure 7. if we use connect the output line O 5 , (instead of O 0 ) of the decoder to the C͞E signal, what will be the memory address range or the circuit? 7. In Figure 7. if we use all the output lines (O 7 -O 0 ) or the decoder to select memory chips of the same size as the 2764 , what is the total range of the memory map ?...

  To read from memory, the address of the register to be read from should be placed on the address lines; arid the Chip Enable C͞E and R͞D signals must be , asserted low to enable the Output buffer. To write into memory, die address of the register to be written into should be placed on the address lines; a data byte should be placed on the data lines, and the Chip Enable C͞E and W͞R signals must be asserted low to enable the input buffer. The Z80 identifies memory operations by initiating the M͞R͞E͞Q signal. This signal is combined with the decoded address pulse (C͞S) generate Memory Select (M͞S͞EL), which is connected to the Chip Enable (C͞E) signal of the memory chip. Another alternative is to use the decoded address pulse C͞S to enable the memory chip and generate Memory Read (M͞E͞M͞R͞D) and Memory Write (M͞E͞M͞W͞R) signals by combining M͞R͞E͞Q , R͞D, and W͞R signals. To interface a memory chip with the Z80, the necessary low-orde...

In the above discussion of memory interfacing, we focused on certain aspects of the communication process between the Z80 and memory. However, in order to avoid distraction from basic concepts, we did not address several important is­sues. Now we will attempt to answer those questions briefly or provide references for them : . . How do you determine whether a memory chip is too slow for a given Z80 system? The response time of a memory chip is defined in terms of Access Time. This is the time delay between when the microprocessor places a memory address on the address bus and when memory places a data byte on the data bus. Typi­cally, Access Time is 50-450 ns for static RIW memory. Similarly, the micropro­cessor has a timing specification: the time delay after the Z80 places an address on the address bus to When it begins to read data on the data bus. The memory access time must be less than this microprocessor time delay. This will be dis. cussed when we consider a...

In the last section, we discussed how to design or interface .memory for a given address. The next step is to test and verify that we can store a byte at a memory location within the address range of the memory chip and read the byte. At this point, we need to make an assumption that we have a working microcomputer system, and the memory design is an expansion of the existing system. If we are designing a system, we may need to use an in-circuit emulator to test the memory; this is discussed in Topic 17. To test the memory, We can simply access an address such as 2800 H through the system keyboard, store a byte, and check the address location again to verify the byte. If there is any fault in the interfacing circuit, 'the system is likely to show an error message, or a different byte from the one we stored will be displayed. Now we need to troubleshoot the interfacing circuit. The question is: Where do we begin? The obvious step is to check the wiring and the pin connections Aft...

In this example, we will use the MOSTEK MK4802 memory chip to demonstrate both Read and Write operations. To simplify the discussion, we will use the same decoding circuit as in Figure 7, except the M͞S͞E͞L 4 signal is used as the Chip Enable. This chip has 2K of memory; therefore, two address lines (A12 and All) have to be left as "don't care" to use the previous circuit. Because of the "don't care" address line, the memory registers will have multiple addresses, and the memory chip will occupy more memory space than necessary (explained later). MOSTEK MK4802 Static R/W Memory This is a 2K static R/W memory chip, organized as 2048 x 8 format. It has eleven address lines (A 10 -A 0 ), eight data lines, and three control signals: C͞E, O͞E: and W͞E. We are already familiar with the first two control signals, and the third signal FIGURE 4.8 MK4802 or CMOS 6116 Static R/W Memory Pin Configuration and Logic Symbol   W͞E (Write Enable), is active ...

In this section, we will illustrate memory interfacing with the Z80 microprocessor by using an actual chip: the 2764 PROM (Erasable Programmable Read-Only- memory). This is a memory chip commonly used in industry to develop microprocessor-based products .. In this illustration, we will assume that the chip bas been already programmed-that is the binary patterns representing Z80 instructions are stored in it-and we will only read from it , we focus only on the interfacing concepts, Interfacing logic circuit, and memory addresses. 2764 EPROM This is an 8K (8192 x 8) memory chip with eight data lines and is housed in a 28-pin package : Figure 6 shows the logic pinout and the pin configuration. It has thirteen address lines, A 12 -A 0 to identify 8192 registers one chip select signal shown as chip enable (C͞E) and one output Enable (O͞E) signal to enable the output buffer. FIGURE 6 2764 EPROM: Pin Configuration and Logic Symbol It operates from a single + 5 V power supply...

In Topic 3, we showed t e timing diagrams and the Z80 bus contents When an opcode or a data byte is fetched from memory. To read from memory, the Z80 performs the following steps, as shown in Figure 2(a) : 1- Places a 16-bit address on its address bus (shown as high- and low order addresses ) 2- Asserts the M͞R͞E͞Q to indicate that the address bus holds a valid address 3- Asserts the R͞D signal low to indicate that it wants to read . To write into memory, the Z80 performs the following steps, as shown in Figure 3: 1- Places a 16-bit address on its address bus 2- Asserts M͞R͞E͞Q and places data on the data bus . 3- Asserts W͞R signal To understand and design an interface circuit, we need to match the memory requirements with the Z80 read/write operations. FIGURE 4.2 (a) Memory Read Timing Diagram; (b) Block Diagram: Address Decoding and Memory Read/Write Operations Basic Concepts in Memory Interfacing The primary function of memory interfacing is to allow the m...

Memory is an integral part of a microprocessor ­based system, and in this topic our focus will be on how to interface a memory chip with the microprocessor. We will examine memory structure and requirements to read from it an write into it, We then compare those require­ments with those of the Z80 Memory Read and Write machine cycles, From that comparison, we will derive the basic steps necessary to in­terface memory. This topic illustrates two .examples of interfacing memory chips, one EPROM and the other static R/W memory. The discussion in­cludes analyses of the following: decoding cir­cuits, memory maps, the concepts of fold back memory and absolute decoding. Finally, an example of memory design is illustrated to synthesize the interfacing concepts. OBJECTIVES List the requirements to read from memory. List the steps initiated by the Z80 to read from and write into memory. List the steps required to interface a memory chip with the Z80. ...