8051 microcontrollers

is an introduction to Z80 assembly language programming. It explains commonly used instructions, elementary pro­gramming techniques and their applications, and the modular approach to software design. The content is presented in a format sim­ilar to one for learning a foreign language. One approach to learning a foreign language is to be­gin with a few words that can form simple, meaningful, and interactive sentences. After learning a few sentences, one begins writing paragraphs that can convey ideas in a coherent fashion; then, by sequencing a few paragraphs, one can compose a letter. Chapters 6 to 11 are arranged in similar fashion-from simple in­structions to applications. . Chapter 6 presents the Z80 programming model and provides an overview of the Z80 in­struction set and its capability. Chapter 7 deals with software development systems and Z80 as­semblers. Chapters 8 and 9 are concerned primarily with the Z80 instructions that occur most frequently. The instructions are not...

ASSIGNMENTS 1. Explain why the number of output ports in peripheral-mapped I/O is re­stricted to 256 ports. 2. In peripheral-mapped I/O, can an input port and an output port have the same port address? 3. If an output and input port can have the same 8-bit address, how does the Z80 differentiate between the ports? 4. Specify the two control signals required to latch data in an output port. 5. Specify the type of pulse required to latch data in the 7475. 6. Are data latched in the 7475 at the leading edge, during the level, or at the trailing edge of the enable (E) signal? 7. If the control signals W̅R̅ and I̅O̅R̅Q̅ are asserted at the same time, can data be latched using only the control signal W̅R̅? 8. If the answer to the previous question is yes, what are potential problems with the interfacing circuit? 9. In Figure 5.4, explain why the LED cathodes rather than anodes are con­nected to the latch. 10. Specify the control signals required to enable an input port. ...

SUMMARY in this chapter, we have examined the machine cycles of the OUT and IN in­structions and derived the basic concepts for interfacing peripheral-mapped I/Os. Similarly, we examined the machine cycles of memory-related data trans­fer instructions and derived the basic concepts for interfacing memory-mapped I/Os. These concepts were illustrated with three examples of interfacing I/O de­vices and one example of interfacing an analog signal. The interfacing concepts can be summarized as follows. Peripheral-Mapped I/O · The OUT is a 2-byte instruction and copies (transfers or sends) data from the accumulator to the addressed port. · When the Z80 executes the OUT instruction, in the third machine cycle it places the output port address on the low-order bus, places data on the data bus, and asserts the control signals I̅O̅R̅Q̅ and W̅R̅. · A latch is generally used to interface output devices. · The IN instruction is a two-byte instruction and copies (transfers or reads) data...

5.9 SOME QUESTIONS AND ANSWERS During the discussion of interfacing I/O devices, we focused on the basic concepts and avoided some details in order to simplify the presentation. We will now at­tempt to answer some of those questions. 1. What are the other I/O instructions in the Z80 instruction set, and how do they differ from the I/O instructions discussed here? The Z80 instruction set includes six output instructions, of which we dis­cussed only one. The remaining five instructions perform various types of output functions: for example, output a byte from any of the registers or from a memory location, or output a block of memory. In these instructions, register C is used to specify the port address and register B can be used as a counter. 2. What are the contents of the high-order bus (A 15 -A 8 ) during the M 3 cycle of the INIOUT instructions? The contents of the high-order bus during the M 3 cycle of the I/O instruc­tions, illustrated in Sections 5.1 and 5.3, are gene...

5.8 TROUBLESHOOTING I/O INTERFACING CIRCUITS In the last several sections, we discussed the interfacing of I/O devices and in­structions to test them. In I11ustrative Example 1(Figure 5.4), the test program includes two instructions that load the byte 97 H into the accumulator and output the byte to port 07 H • If we execute these instructions and no change is observed at the output port, we must implement the troubleshooting technique similar to that which we used for troubleshooting memory interfacing circuits in the last chapter. After checking the wiring and the pin connections, we can write a diag­nostic routine and execute it in a continuous loop to generate a constant and iden­tifiable signal, and then check various points in relation to that signal. DIAGNOSTIC ROUTINE AND MACHINE CYCLES We can use the same instructions for the diagnostic routine that we used in Illus­trative Example 1; however, to generate a continuous signal, we need to .add a Jump instruction, as shown...

5.7 ADDITIONAL ILLUSTRATIVE EXAMPLES: INTERFACING SENSORS AND MOTORS In previous examples, we illustrated the interfacing of I/O devices that were pri­marily binary devices (on/off). We now extend the concepts to interface analog devices such as temperature sensors and motors. In interfacing analog devices, the basic procedure remains similar to that of interfacing binary devices; the MPU identifies the device through a binary port address and enables it with an appro­priate control signal. However, we need to find a way to detect and to convert the analog signal into the binary format and vice versa. The analog signal is generally handled in two ways: one is to detect the signal when it reaches a predetermined level, and the other is to convert it into binary format proportional to its magni­tude. The predetermined level of the analog signal can be detected by using a comparator circuit, and the binary equivalent can be obtained by using an AID (Analog-to-Digital) data converter. ...

ILLUSTRATIVE EXAMPLE 3: APPLIANCE CONTROL USING MEMORY-MAPPED I/O TECHNIQUE Figure 5.10 shows a schematic of interfacing I/O devices using the memory ­mapped I/O technique. The circuit includes one input port with eight DIP switches and one output port to control the appliances. The appliances are turned on and off by the microprocessor according to the corresponding switch positions. For example, the switch S 7 controls the air conditioner and the switch S 0 controls Light 4. All switch inputs are tied high; therefore, when a switch is open (off), it has + 5 V, and when a switch is closed (on), it has logic 0. The circuit includes two 3-to-8 decoders and one 8-input NAND gate to decode the address bus and generate the control signals. The eight switches are interfaced using a tri-state buffer 74LS244, and the appliances are interfaced using an octal latch (74LS373) with tri-state output. 5.6.1 Control Signals In a memory-mapped I/O circuit, the control signals required are M...

5.5 MEMORY-MAPPED I/O In, memory-mapped I/O, the input and output devices are assigned and identified by 16-bit addresses. To transfer data between the microprocessor and I/O devices, memory- related instructions (such as LD A, (16-bit) and memory control signals (such as M̅R̅E̅Q̅) are used. The microprocessor communicates with an I/O device as if it were one of the memory locations. 5.5.1 Memory-Related Data Transfer Instructions To understand the memory-mapped I/O technique, we need to examine how a data byte is transferred from the Z80 to a memory location or vice versa. For example, the following instruction will transfer (copy) the contents of the accu­mulator to the memory location 8000 H • It is assumed here that the instruction is stored in memory locations 2050 H , 51 H , and 52 H • This is a 3-byte instruction; the first byte is the opcode, and the second and the third bytes specify the memory address. However, the 16-bit address 8000 H is entered in the revers...

ILLUSTRATIVE EXAMPLE 2: INTERFACING INPUT SWITCHES In this section, we will analyze the circuit used for interfacing eight DIP switches as shown in Figure 5.8. The circuit includes the 74LS138 3-to-8 decoder to decode the low-order bus and the tri-state octal buffer (74LS244) to interface the switches to the data bus. The port can be accessed with the address 84 H ; however, it also has multiple addresses. 5.4.1 Hardware Figure 5.8 shows the 74LS244 tri-state octal buffer used as an interfacing device. The device has two groups of four buffers each, and they are controlled by the active low signal O̅E̅ .When O̅E̅ is low, the input data appear on the output lines, and when O̅E̅ is high, the output lines assume high impedance state. 5.4.2 Interfacing Circuit Figure 5.8 shows that the low-order address bus (with the exception of lines A 4 and A 3 ) is connected to the decoder 74LS138; the address lines A 4 and A 3 are left in the "don't care" state. Th...

5.3 INTERFACING INPUT DEVICES The interfacing of input devices is almost identical to that of interfacing output devices, but with some differences in bus signals and circuit components. In this discussion, we will assume that you are familiar with the basic concepts of inter­facing (Section 5.1.3) and describe only the additional details. First, we examine the execution and timing of the IN instruction and discuss the interfacing of input devices in relation to the timing diagram. 5.3.1 IN Instruction The Z80 instruction set includes several instructions to read (copy) data from such. Input devices as switches, keyboards, and A/D data converters. These instruc­tions can read an input device and place the data into the accumulator, Z80 reg­isters, or memory registers. These are two-byte instructions; the first byte is the opcode, and the second byte specifies the port address. Although there are numerous ways of specifying the port address, it is always eight bits long. Thus, th...

5.2 ILLUSTRATIVE EXAMPLE 1: INTERFACING LEDS In this section, we will analyze an actual interfacing circuit with the port address 07 H to display binary data at an LED port and a single digit at a seven-segment LED. A group of 8 LEDs will be used to indicate binary I s and Os and will be' connected to the data bus using the 7475 latches. Similarly, an interfacing of a seven-segment LED will be demonstrated using an octal latch 74LS373. 5.2.1 Hardware Figure 5.3 shows the logic symbols of the 7475 latch. It has four bistable latches controlled by the active high enable signals; E 1 _ 2 enables the first two latches and E 3-4 enables the remaining two. When E is high, data enter the latch and appear at the Q outputs, and Q outputs correspond to the input data, When E goes from high to low, data will be latched and will remain stable until E goes high again. . When Q output is high, it can supply (source) 400 µA, and when it is low, it can sink 16 mA current. Since most LED...

5.1.3 Basic Concepts in Interfacing Output Devices The concepts in interfacing output devices are similar to those in interfacing mem­ory. The steps can be listed as follows: 1. Decode the low-order address bus to generate a unique pulse corresponding to the port address on the bus; this is called the I/O address (I͞O͞A͞D͞R͞) pulse. 2. Combine (AND) the I/O address pulse (I͞O͞A͞D͞R͞), I͞͞O͞R͞Q͞ , and W͞͞R͞ to generate the IOSEL (I/O select) pulse (Figure 5.2(a)). Another approach is to generate the I͞O͞W͞͞R͞ (I/O Write) by combining I͞͞O͞R͞Q͞ and W͞͞R͞, and then combine I͞O͞W͞͞R͞ with the I͞O͞A͞D͞R͞ (I/O Address) pulse to generate the IOSEL pulse (Figure 5.2(b)). The critical concept here is that the decoded address, I͞͞O͞R͞Q͞, and W͞͞͞R͞ are all necessary to latch the data at the appropriate time; how these signals are combined is often dictated by availability of decoding devices (chips) in the system. 3. Use the IOSEL pulse to enable (activate) the output device. Let us ex...

Interfacing I/O Devices The I/O (Input/Output) is the third component of a microprocessor-based system. I/O devices, such as keyboards and displays, are the ears and eyes of the MPUs; they are the communi­cation channels to the "outside world." Data can enter or exit in groups of eight bits using the entire data bus; this is called the parallel I/O mode. The other mode is the serial I/O, whereby one bit is transferred using one data line; typical examples include peripherals such as CRT ter­minals or cassette tapes. In this chapter, we fo­cus on interfacing I/O devices in the parallel mode; the serial mode will be discussed in the topic. In the parallel I/O mode, devices can be interfaced using two techniques: peripheral mapped I/O and memory-mapped I/O. In peripheral-mapped I/O, a device is identified with an 8-bit address and enabled by I/O-related control signals. In memory-mapped I/O, a de­vice is identified with a 16-bit address and en­abled by memory-related control...