8051 microcontrollers

QUESTIONS AND PROBLEMS 10.1 What are the basic differences between the 68000,68008,68010, and 68012? 10.2 What D0es a HIGH on the 68000 FC2 pin indicate? 10.3 (a) If a 68000-based system operates in the user mode and an interrupt occurs, what will the 68000 mode be? (b) If a 68000-based system operates in the supervisor mode, how can the mode be changed to user mode? 10.4 (a)  What is the purpose of 68000 trace and X flags? (b) How can you set or reset them? 10.5 Indicate whether the following 68000 instructions are valid or not valid. Justify your answers. 10.6 How many addressing modes and instructions D0es the 68000 have? 10.7 What happens after execution of the following 68000 instruction? MOVE.L D0,$03000013 10.8 What is meant by 68000 privileged instructions? 10.9 Identify the following 68000 instructions as privileged or nonprivileged: 10.11 Identify the addressing modes for each of the following 68000 instructions: (a) CLR D0 ...

10.13 68000 Exception Handlin : A 16-bit microcomputer is usually capable of hanD1ing unusual or exceptional conditions. These conditions include situations such as execution of illegal instruction or division by zero. In this section, the exception-hanD1ing capabilities of the 68000 are described. The 68000 exceptions can be divided into three groups, namely, groups 0, 1, and 2. Group 0 has the highest priority, and group 2 has the lowest priority. Within each group, there are additional priority levels. A list of 68000 exceptions along with individual priorities is as follows: Group 0 Reset (highest level in this group}, address error (next level), and bus error (lowest level) Group 1 Trace (highest level), interrupt (next level), illegal op-code (next level), and privilege violation (lowest level) Group 2 TRAP, TRAPV, CHK, and ZERO DIVIDE (no individual priorities assigned in group 2) Exceptions from group 0 always override an active exception from group 1 or group 2. ...

10.10 68000 Memory Interface One of the advantages of the 68000 is that it can easily be interfaced to memory chips with various speeds because it goes into a wait state if DTACK is not asserted (LOW) by the memory devices at the end of S4. A simplified schematic showing an interface of a 68000 to two 2732's and two 6116's is given in Figure 10.15. As mentioned in Chapter 9, the 2732 is a 4K x 8 EPROM and the 6116 is a 2K x 8 static RAM. The pin diagrams of the 6116 and 2732 are provided in Appendices C and E respectively. For a 4-MHz clock, each cycle is 250 ns. Because the 68000 samples data at the falling edge of S4 (750 ns) and latches data at the falling edge of S6 (1000 ns), AS can be used to assert DTACK. From the 68000 timing diagram of Figure 10.13, AS goes to LOW after approximately two cycles (500 ns). The time delay between AS going LOW and the falling edge of S6 is 500 ns. Note that LDS and UDS must be used as chip selects as in Figure 10.15. They must not be con...

10.9 68000 Clock and Reset Signals This section covers generation of 68000 clock and reset signals in detail because the clock signal and the reset pins are two important signals of any microprocessor. 10.9.1 68000 Clock Signals As mentioned before, the 68000 D0es not include an on-chip clock generation circuitry. This means that an external crystal oscillator chip is required to generate the clock. The 68000 CLK input can be provided by a crystal oscillator or by designing an external circuit. Figure 10.10 shows a simple oscillator to generate the 68000 CLK input. This circuit uses two inverters connected in series. Inverter 1 is biased in its transition region by the resistor R. Inverter I inputs the crystal output (sinusoidal) to provide a logic pulse train at the output of inverter 1. Inverter 2 sharpens the wave and drives the crystal. For this circuit to work, HCMOS logic for the inverters must be used. Therefore, the 74HC04 inverter chip is used. The 74HC04 has hig...