8051 microcontrollers

QUESTIONS AND PROBLEMS 11.1 Discuss the typical features of 32-bit and 64-bit microprocessors. 11.2 (a) What is the basic difference between the 80386 and 80386SX? (b) What is the basic difference between the 80386 and 80486? 11.3 What is the difference between the 80386 protected, real-address, and virtual 8086 modes? 11.4 Discuss the basic features of the 80486. 11.5 Assume the following 80386 register contents (EBX) = 00001000H (ECX)=04000002H (EDX) = 20005000H prior to execution of each of the following 80386 instructions. Determine the contents of the affected registers and/or memory locations after execution of each of the following instructions and identify the addressing modes: (a) MOV        [EBX * 4]        [ECX],         EDX (b) MOV       [EBX * 2]        [ECX + 2020H],...

11.7.2 Motorola's State-of-the-art Microprocessors As part of their plans to carry the PowerPC architecture into the future, Motorola /IBM/ Apple already announced AltiVec extensions for the PowerPC family. The result is the MPC7400 PowerPC microprocessor. This microprocessor is available in 400 MHz, 450 MHz and 500 MHz clock speeds. Motorola's AltiVec technology is the foundation for the Velocity Engine of Apple Computer's next generation desktop computers. For example, Apple rececently announced Power Mac G5 which uses Motorola's 64-bit microprocessor, G5. AltiVec extensions are somewhat comparable to the MMX extensions in Intel's Pentium family. AltiVec has independent processing units while Intel tied MMX to the floating-point unit. Both utilize SIMD (Chapter 8). A comparison of some of the features of AltiVec vs. MMX is provided below: In AltiVec, each processing unit can work independent of the others. This provides more parallelism by separate units. ...

11.7.2 Motorola MC68030 The MC68030 is a virtual memory microprocessor based on the MC68020 with additional features. The MC68030 is designed by using HCMOS technology and can be operated at clock rates of 16.67 and 33 MHz. The MC68030 contains all features of the MC68020, plus some additional ones. The basic differences between the MC68020 and MC68030 are as follows: 11.7.3 Motorola MC68040 I MC68060 This section presents an overview of the Motorola MC68040 and MC 68060 32-bit microprocessors. The MC68040 is Motorola's enhanced 68030, 32-bit microprocessor, implemented in HCMOS technology. Providing balance between speed, power, and physical device size, the MC68040 integrates on-chip MC68030-compatible integer unit, an MC68881/ MC68882-compatible floating-point unit (FPU), dual independent demand­ paged memory management units (MMUs) for instruction and data stream accesses, and an independent 4 KB instruction and data cache. A high degree of instruction execution paralle...

Example 11.8 Determine the effect of execution of each of the following PACK and UNPK instructions: Assume the following data prior to execution of each of the above instructions: Note that ASCII code for 2 is $32 and for 7 is $37. Hence, this pack·instruction converts ASCII code to packed BCD. PACK -(Al),-(A4),$0000 (EA) can use all modes except An. The condition codes N: Z. and V are affected; C is always cleared to 0, and X is unaffected for both MULS and MULU. For signed multiplication, overflow (V = I) can only occur for 32 x 32 multiplication, producing a 32-bit result if the high-order 32 bits of the 64-bit product are not the sign extension of the low-order 32 bits. In the case of unsigned multiplication, overflow (V = I) can occur for 32 x 32 multiplication, producing a 32-bit result if the high-order 32 bits of the 64-bit product are not zero. Both MULS and MULU have a word form and a long word form. For the word form ( 16 x 16), the multiplier and multi...

MC68020 System Design The following 8-MHz 68020 system design will use a 128 KB 32-bit wide supervisor data memory. Four 27C256's (32K x 8 HCMOS EPROM with 120-ns access time) are used for this purpose. Because the memory is 32 KB, the 68020 address lines A2-A16 are used for addressing the 27C256' s. The 68020 SIZ1, SIZ0, A 1, A0, DSACK 1, and DSACK0 pins are utilized for selecting the memory chips. Table 11.12 shows the table for designing the enable logic for the four 27C256 chips. The 68020 A 17 pin is used to distinguish between memory and I/O. A 17 = 0 is used to select the memory chips; A 17 = 1 is used to select I/O chips (not shown in the design). Table 11.13 shows the K-maps for the enable logic. A logic diagram can be drawn for generating the memory byte enable signals DBBE1, DBBE2, DBBE3, and DBBE4. The 68020 system with 32-bit memory consists offour 27C256's, each connected to its associated portion of the system data bus (D 31 -D 24 , D 23 -D 16 , D 15...