8051 microcontrollers

1. if a memory chip is organized in a 4096 x 1 format, specify the number of registers in the chip and the number of bits stored by each register. 2. if 16K x 1 memory chips are used in a memory design, how many chips are required to design 64K-byte memory? 3. Specify the number of chips necessary to design 8K-byte memory with 1024 x 4 memory chips. 4. In Figure 1 . generate the equivalent M͞S͞EL 0 " signal by using a4-input NAND gate (and inverters) to decode the address lines A 15 -A 13 and the M͞R͞E͞Q. 5. Generate the signal equivalent to the M͞S͞E͞L 0 signal in Figure 7 using the 74LS139. which bas two 2-to-4 decoders in the package. 6. In Figure 7. if we use connect the output line O 5 , (instead of O 0 ) of the decoder to the C͞E signal, what will be the memory address range or the circuit? 7. In Figure 7. if we use all the output lines (O 7 -O 0 ) or the decoder to select memory chips of the same size as the 2764 , what is the total range of the memory map ?...

  To read from memory, the address of the register to be read from should be placed on the address lines; arid the Chip Enable C͞E and R͞D signals must be , asserted low to enable the Output buffer. To write into memory, die address of the register to be written into should be placed on the address lines; a data byte should be placed on the data lines, and the Chip Enable C͞E and W͞R signals must be asserted low to enable the input buffer. The Z80 identifies memory operations by initiating the M͞R͞E͞Q signal. This signal is combined with the decoded address pulse (C͞S) generate Memory Select (M͞S͞EL), which is connected to the Chip Enable (C͞E) signal of the memory chip. Another alternative is to use the decoded address pulse C͞S to enable the memory chip and generate Memory Read (M͞E͞M͞R͞D) and Memory Write (M͞E͞M͞W͞R) signals by combining M͞R͞E͞Q , R͞D, and W͞R signals. To interface a memory chip with the Z80, the necessary low-orde...

In the above discussion of memory interfacing, we focused on certain aspects of the communication process between the Z80 and memory. However, in order to avoid distraction from basic concepts, we did not address several important is­sues. Now we will attempt to answer those questions briefly or provide references for them : . . How do you determine whether a memory chip is too slow for a given Z80 system? The response time of a memory chip is defined in terms of Access Time. This is the time delay between when the microprocessor places a memory address on the address bus and when memory places a data byte on the data bus. Typi­cally, Access Time is 50-450 ns for static RIW memory. Similarly, the micropro­cessor has a timing specification: the time delay after the Z80 places an address on the address bus to When it begins to read data on the data bus. The memory access time must be less than this microprocessor time delay. This will be dis. cussed when we consider a...

In the last section, we discussed how to design or interface .memory for a given address. The next step is to test and verify that we can store a byte at a memory location within the address range of the memory chip and read the byte. At this point, we need to make an assumption that we have a working microcomputer system, and the memory design is an expansion of the existing system. If we are designing a system, we may need to use an in-circuit emulator to test the memory; this is discussed in Topic 17. To test the memory, We can simply access an address such as 2800 H through the system keyboard, store a byte, and check the address location again to verify the byte. If there is any fault in the interfacing circuit, 'the system is likely to show an error message, or a different byte from the one we stored will be displayed. Now we need to troubleshoot the interfacing circuit. The question is: Where do we begin? The obvious step is to check the wiring and the pin connections Aft...

In this example, we will use the MOSTEK MK4802 memory chip to demonstrate both Read and Write operations. To simplify the discussion, we will use the same decoding circuit as in Figure 7, except the M͞S͞E͞L 4 signal is used as the Chip Enable. This chip has 2K of memory; therefore, two address lines (A12 and All) have to be left as "don't care" to use the previous circuit. Because of the "don't care" address line, the memory registers will have multiple addresses, and the memory chip will occupy more memory space than necessary (explained later). MOSTEK MK4802 Static R/W Memory This is a 2K static R/W memory chip, organized as 2048 x 8 format. It has eleven address lines (A 10 -A 0 ), eight data lines, and three control signals: C͞E, O͞E: and W͞E. We are already familiar with the first two control signals, and the third signal FIGURE 4.8 MK4802 or CMOS 6116 Static R/W Memory Pin Configuration and Logic Symbol   W͞E (Write Enable), is active ...

In this section, we will illustrate memory interfacing with the Z80 microprocessor by using an actual chip: the 2764 PROM (Erasable Programmable Read-Only- memory). This is a memory chip commonly used in industry to develop microprocessor-based products .. In this illustration, we will assume that the chip bas been already programmed-that is the binary patterns representing Z80 instructions are stored in it-and we will only read from it , we focus only on the interfacing concepts, Interfacing logic circuit, and memory addresses. 2764 EPROM This is an 8K (8192 x 8) memory chip with eight data lines and is housed in a 28-pin package : Figure 6 shows the logic pinout and the pin configuration. It has thirteen address lines, A 12 -A 0 to identify 8192 registers one chip select signal shown as chip enable (C͞E) and one output Enable (O͞E) signal to enable the output buffer. FIGURE 6 2764 EPROM: Pin Configuration and Logic Symbol It operates from a single + 5 V power supply...

In Topic 3, we showed t e timing diagrams and the Z80 bus contents When an opcode or a data byte is fetched from memory. To read from memory, the Z80 performs the following steps, as shown in Figure 2(a) : 1- Places a 16-bit address on its address bus (shown as high- and low order addresses ) 2- Asserts the M͞R͞E͞Q to indicate that the address bus holds a valid address 3- Asserts the R͞D signal low to indicate that it wants to read . To write into memory, the Z80 performs the following steps, as shown in Figure 3: 1- Places a 16-bit address on its address bus 2- Asserts M͞R͞E͞Q and places data on the data bus . 3- Asserts W͞R signal To understand and design an interface circuit, we need to match the memory requirements with the Z80 read/write operations. FIGURE 4.2 (a) Memory Read Timing Diagram; (b) Block Diagram: Address Decoding and Memory Read/Write Operations Basic Concepts in Memory Interfacing The primary function of memory interfacing is to allow the m...

Memory is an integral part of a microprocessor ­based system, and in this topic our focus will be on how to interface a memory chip with the microprocessor. We will examine memory structure and requirements to read from it an write into it, We then compare those require­ments with those of the Z80 Memory Read and Write machine cycles, From that comparison, we will derive the basic steps necessary to in­terface memory. This topic illustrates two .examples of interfacing memory chips, one EPROM and the other static R/W memory. The discussion in­cludes analyses of the following: decoding cir­cuits, memory maps, the concepts of fold back memory and absolute decoding. Finally, an example of memory design is illustrated to synthesize the interfacing concepts. OBJECTIVES List the requirements to read from memory. List the steps initiated by the Z80 to read from and write into memory. List the steps required to interface a memory chip with the Z80. ...

1- The MOS Technology 6501 microprocessor chip has 13 address lines. Spec­ify the memory registers it is capable of addressing. 2- If the Intel 8086 microprocessor has 20 address lines, what is its capacity of memory addressing? 3- Explain the functions of the accumulator. 4- List the Z80 programmable registers. 5- What is a flag? 6- What is the function of the program counter? 7- If the Z80 is executing the code fetched from the memory location 1845 H , what is the memory address in the program counter? 8- If the clock frequency is 4 MHz, how much time is required to execute an instruction of 21 T-states? 9- The instruction LD IX, (2050 H ) loads 2050 H into the index register. Specify the number of bytes. machine cycles, and T-states of this instruction by checking the instruction set. Calculate the time required to execute the in­struction if the system clock frequency is 6 MHz. 10- List the sequence of events that occurs when the Z80 reads from memory. 11- In t...

· The Z80 signals can be classified into six groups: address bus, data bus, con­trol signals, external requests, request acknowledge, and power and frequency signals (see section 1 for definitions of these signals). · The Z80 address bus has 16 unidirectional address lines; they are capable of addressing 64K memory. · The Z80 data bus has eight bidirectional data lines, and they are used for data transfer. · The Z80 microprocessor has six general-purpose 8-bit registers IB, C. D. E, H, and L) as a primary set. In addition, it includes the alternate set of these registers that can be used to exchange information with the primary set. The registers Band C, D and E, and Hand L can be combined to perform Some 16-bit operations. · The ALU section of the Z80 includes accumulator A and the flag register to indicate six different data conditions. It also includes the alternate accumula­tor A' and the flag register F', which can be used to exchange information with A and F, re...

The primary reasons to discuss other 8-bit microprocessors are to examine how the MPU model developed in the last topic matches with various microproces­sors and to confirm that the underlying basic concepts remain similar even though specific details may vary from one chip to another. At present. many 8-bit general-­purpose microprocessors are available in the market. We will focus on three: the Intel 8085. the National Semiconductor NSC 800, and the Motorola 6800. These microprocessors are selected to illustrate various strategies used in designing the microprocessor. The recent trend in 8-bit microprocessors can be illustrated by so-called 8-bit super chips, such as the Hitachi HD64180, discussed in Topic 18. Inte18085 The intel 8085 and its predecessor the 8080 are widely used 8-bit microprocessors. The 8080 MPU is composed of three chips-the 8080 microprocessor, the clock generator, and the system driver-and it needs three power supplies ( + 5 V, - 5 V. + 12 V). The 8085 is an...

After reading the previous sections. the reader may have many unanswered ques­tions. One of the primary reasons for this predicament is that the microprocessor is a programmable and complex device. It interacts with external devices such as memory and I/Os. and some questions cannot be answered until we discuss these other devices. Similarly. some questions will remain unanswered until we start using instructions and writing programs. However. there are some questions that we should answer immediately.  1. How does the Z80 microprocessor know where to begin after the power is turned on? Most microcomputer systems have built-in power-on reset circuits , meaning that when the power is turned on, the microprocessor is reset and its program counter is cleared to the address 0000 H , address 0000 H is placed on the address bus and the instruction stored at that location determines what happens next. 2. How does the Z80 know what operation to perform first (Memory Read/Writ...

After examining the concepts summarized at the end of the previous section, we may need to generate additional control signals. 1. To read from memory, the M͞R͞E͞Q and the R͞D signals are necessary, and to read from an input device, the I͞O͞R͞Q and the R͞D are necessary; all these sig­nals are active low. As a design practice, the M͞R͞E͞Q is generally combined with a decoded address (discussed in Topic4). and R͞D is connected directly to the memory chip. However, control signals R͞D and W͞R can also be com­bined with M͞R͞E͞Q and I͞O͞R͞Q to generate additional signals. We can generate active low Memory Read (M͞E͞M͞R͞D) signal either by ANDing these signals in a negative NAND gate as shown in Figure 7(a) or by using a 2-to-4 decoder as shown in Figure 7(b). The decoder is enabled by the M͞R͞E͞Q and has R͞D and W͞R signals as input. Both inputs cannot be active at the same time; when one is low, the other will remain high, When R͞D is active low, the input is 0 1 , and the output O 1 g...