SUMMARY OF MEMORY INTERFACING

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MEMORY INTERFACING

  • To read from memory, the address of the register to be read from should be placed on the address lines; arid the Chip Enable C͞E and R͞D signals must be , asserted low to enable the Output buffer.
  • To write into memory, die address of the register to be written into should be placed on the address lines; a data byte should be placed on the data lines, and the Chip Enable C͞E and W͞R signals must be asserted low to enable the input buffer.
  • The Z80 identifies memory operations by initiating the M͞R͞E͞Q signal. This signal is combined with the decoded address pulse (C͞S) generate Memory Select (M͞S͞EL), which is connected to the Chip Enable (C͞E) signal of the memory chip. Another alternative is to use the decoded address pulse C͞S to enable the memory chip and generate Memory Read (M͞E͞M͞R͞D) and Memory Write (M͞E͞M͞W͞R) signals by combining M͞R͞E͞Q , R͞D, and W͞R signals.
  • To interface a memory chip with the Z80, the necessary low-order address lines of the Z80 address bus are connected to the address lines Of the memory chip. The high-order address lines and the M͞R͞E͞Q are used to generate to M͞S͞EL signal, which enables the chip. The R͞D signal is used to enable the output buffer and the W͞R signal is used to write into memory by enabling the input buffer .
  • In the absolute decoding technique, all the address lines not used by a mem­ory chip to identify a memory register must be decoded; thus, die Chip Select can be asserted by only one address. In the partial decoding technique, some address lines can be left as '''don't care. " This technique saves on hardware. Out generates multiple addresses, which result in foldback memory space.
  • To troubleshoot an interfacing circuit, a constant and identifiable signal must be generated by writing a continuous loop.

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