8051 microcontrollers

NEW PENTIUM INSTRUCTIONS The Pentium contains only one new instruction that functions with normal system software; the remainder of the new instructions are added to control the memory-management mode feature and serializing instructions. Table 18–3 lists the new instructions added to the Pentium instruction set. The CMPXCHG8B instruction is an extension of the CMPXCHG instruction added to the 80486 instruction set. The CMPXCHG8B instruction compares the 64-bit number stored in EDX and EAX with the contents of a 64-bit memory location or register pair. For example, the CMPXCHG8B DATA2 instruction compared the eight bytes stored in memory location DATA2 with the 64-bit number in EDX and EAX. If DATA2 equals EDX:EAX, the 64-bit number stored in ECX:EBX is stored in memory location DATA2. If they are not equal, the contents of DATA2 are stored into EDX:EAX. Note that the zero flag bit indicates that the contents of EDX:EAX were equal or not equal to DATA2. The CPUID instruction read...

PENTIUM MEMORY MANAGEMENT The memory-management unit within the Pentium is upward-compatible with the 80386 and 80486 microprocessors. Many of the features of these earlier microprocessors are basically unchanged in the Pentium. The main change is in the paging unit and a new system memory- management mode. Paging Unit The paging mechanism functions with 4K-byte memory pages or with a new extension available to the Pentium with 4M-byte memory pages. As detailed in Chapters 1 and 17, the size of the paging table structure can become large in a system that contains a large memory. Recall that to fully repage 4G bytes of memory, the microprocessor requires slightly over 4M bytes of memory just for the page tables. In the Pentium, with the new 4M-byte paging feature, this is dramatically reduced to just a single page directory and no page tables. The new 4M-byte page sizes are selected by the PSE bit in control register 0. The main difference between 4K paging and 4M paging is that...

SPECIAL PENTIUM REGISTERS The Pentium is essentially the same microprocessor as the 80386 and 80486, except that some additional features and changes to the control register set have occurred. This section highlights the differences between the 80386 control register structure and the flag register. Control Registers Figure 18–8 shows the control register structure for the Pentium microprocessor. Note that a new control register, CR4, has been added to the control register array. This section of the text only explains the new Pentium components in the control registers. See Figure 17-14 for a description and illustration of the 80386 control registers. Following is a description of the new control bits and new control register CR4: CD Cache disable controls the internal cache. If CD = 1, the cache will not fill with new data for cache misses, but it will continue to function for cache hits. If CD = 0, misses will cause the cache to fill with new data. NW Not write-throu...

THE PENTIUM AND PENTIUM PRO MICROPROCESSORS INTRODUCTION The Pentium microprocessor signals an improvement to the architecture found in the 80486 microprocessor. The changes include an improved cache structure, a wider data bus width, a faster numeric coprocessor, a dual integer processor, and branch prediction logic. The cache has been reorganized to form two caches that are each 8K bytes in size, one for caching data, and the other for instructions. The data bus width has been increased from 32 bits to 64 bits. The numeric coprocessor operates at approximately five times faster than the 80486 numeric coprocessor. A dual integer processor often allows two instructions per clock. Finally, the branch prediction logic allows programs that branch to execute more efficiently. Notice that these changes are internal to the Pentium, which makes software upward-compatible from earlier Intel 80X86 microprocessors. A later improvement to the Pentium was the addition of the MMX instructions. ...

QUESTIONS AND PROBLEMS 1. The 80386 microprocessor addresses bytes of memory in the protected mode. 2. The 80386 microprocessor addresses bytes of virtual memory through the memory-management unit. 3. Describe the differences between the 80386DX and the 80386SX. 4. Draw the memory map of the 80386 when operated in the (a) protected mode (b) real mode 5. How much current is available on various 80386 output pin connections? Compare these currents with the currents available at the output pin connection of an 8086 microprocessor. 6. Describe the 80386 memory system, and explain the purpose and operation of the bank selection signals. 7. Explain the action of a hardware reset on the address bus connections of the 80386. 8. Explain how pipelining lengthens the access time for many memory references in the 80386 microprocessor-based system. 9. Briefly describe how the cache memory system functions. 10. I/O ports in the 80386 start at I/O address ____________ ...

SUMMARY 1. The 80386 microprocessor is an enhanced version of the 80286 microprocessor and includes a memory-management unit that is enhanced to provide memory paging. The 80386 also includes 32-bit extended registers, and a 32-bit address and data bus. A scaled-down version of the 80386DX with a 16-bit data and 24-bit address bus is available as the 80386SX micro- processor. The 80386EX is a complete AT-style personal computer on a chip. 2. The 80386 has a physical memory size of 40 bytes that can be addressed as a virtual memory with up to 64T bytes. The 80386 memory is 32 bits wide, and it is addressed as bytes, words, or double words. 3. When the 80386 is operated in the pipelined mode, it sends the address of the next instruction or memory data to the memory system prior to completing the execution of the current instruction. This allows the memory system to begin fetching the next instruction or data before the current is completed. This increases access time, thus reducing...

THE MEMORY PAGING MECHANISM The paging mechanism allows any linear (logical) address, as it is generated by a program, to be placed into any physical memory page, as generated by the paging mechanism. A linear memory page is a page that is addressed with a selector and an offset in either the real or protected mode. A physical memory page is a page that exists at some actual physical memory location. For example, linear memory location 20000H could be mapped into physical memory location 30000H, or any other location, with the paging unit. This means that an instruction that accesses location 20000H actually accesses location 30000H. Each 80386 memory page is 4K bytes long. Paging allows the system software to be placed at any physical address with the paging mechanism. Three components are used in page address translation: the page directory, the page table, and the actual physical memory page. Note that EEM386.EXE, the extended memory manager, uses the paging mechanism to simul...